In a synchronous memory device represented by a synchronous DRAM, a DLL circuit is used to correctly synchronize an output timing of a read data with an external clock signal. An output clock signal generated by the DLL circuit is supplied to an output buffer via a clock tree. When an internal clock signal with a high frequency propagates to the clock tree, current consumption increases. Accordingly, in a period in which no read data is output, the DLL circuit is stopped or the frequency of the internal clock signal is lowered to reduce the current consumption.
In a method of stopping the DLL circuit during a period in which no read data is output, the DLL circuit is periodically activated to correct misalignment of the output clock signal caused by PVT fluctuations. In a method of lowering the frequency of the internal clock signal during a period in which no read data is output, the internal clock signal is divided by a clock divider.
The DLL circuit includes a phase detector to determine the phases of the external clock signal and the internal clock signal. When the phase detector is placed at a subsequent stage of the clock divider, the phase detector cannot determine the phases in some relations between a division ratio of the clock divider and a DLL forward path delay.